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[Other] 1.6运算器部件实验：乘法器

Description: 这个是用vhdl编写的乘法器,仅仅供大家参考-VHDL prepared by the multiplier, just for reference
Platform: | Size: 150162 | Author: 李乐雅 | Hits:

[Other resource] booth_mul

Description: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL.
Platform: | Size: 19758 | Author: 李鹏 | Hits:

[Other resource] Booth_Multiplier

Description: 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
Platform: | Size: 1796 | Author: 韓堇 | Hits:

[Other resource] mul6

Description: 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English
Platform: | Size: 463599 | Author: qindao | Hits:

[Other resource] add_multi

Description: 移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件-displacement add hardware multiplier, based on FPGA VHDL prepared, containing all the documents
Platform: | Size: 3466 | Author: 相耀 | Hits:

[Other resource] BoothMultiplier

Description: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier -- This file contains a ll the entity-architectures for a complete -- k - bit x k-bit Booth multiplier. -- the design mak es use of the new shift operators available in th e VHDL-93 std -- this design passes the Synplify synthesis check -- download from : www.fpga.com.cn
Platform: | Size: 1833 | Author: 罗兰 | Hits:

[Other resource] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
Platform: | Size: 179551 | Author: 李中伟 | Hits:

[Other] 15_MUX41

Description: 乘法器，用VHDL语言编码，可能对你用处不是很大，但做为参考还是很大用处的-multiplier using VHDL coding, you may not have much use, but as a reference or very useful
Platform: | Size: 6785 | Author: jinlong | Hits:

[Other resource] shixuchengfa

Description: 时序乘法器,8位x8位,vhdl语言.仿真验证过了.多多交流!-sequential multiplier, eight x8 spaces vhdl language. Simulation before. Interact more!
Platform: | Size: 1847 | Author: 天禄 | Hits:

[Other] Multiplier

Description: 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is set by the parameter, you can modify. I have written a testbench. Ease of use.
Platform: | Size: 169984 | Author: ljt | Hits:

[Other Embeded program] Hardware-multiplier

Description: 基于VHDL的硬件乘加器设计,包括QUARTERS 的文件以及实验报告,便于参考和修改-Hardware multiplier design based on VHDL, including the QUARTERS file as well as the experimental report, ease of reference and modification
Platform: | Size: 965632 | Author: amos | Hits:

[VHDL-FPGA-Verilog] VHDL-Samples

Description: VHDL Samples，8-bit calculator controller；vending machine controller with typical vending machine logic ；mplements (most of) the logic required to implement a IEEE 754 multiplier unit.
Platform: | Size: 542720 | Author: 小海豚 | Hits:

[Other] VHDL

Description: GCD and Booth Multiplier VHDL code
Platform: | Size: 1328128 | Author: Sat | Hits:

[VHDL-FPGA-Verilog] mac_accumulator

Description: VHDL Multiplier Adder Accumulator together with Test Bench.
Platform: | Size: 1024 | Author: AhMahdi | Hits:

[VHDL-FPGA-Verilog] multiplier_n_bits

Description: VHDL multiplier - input : two n (n customizable) bits width vectors
Platform: | Size: 4096 | Author: croissant | Hits:

[Other] booth

Description: it's booth vhdl code for DE2 altra boards
Platform: | Size: 549888 | Author: hosseinkhani | Hits:

[Other] multiply

Description: it's a simple multiplier in vhdl language
Platform: | Size: 1049600 | Author: hosseinkhani | Hits:

[Other] wallace and truncated 4 8 12

Description: wallace multiplier 4, 8,12 bits
Platform: | Size: 10240 | Author: bangaram | Hits:

[VHDL-FPGA-Verilog] Assignment_2_ver.3

Description: Small ALU with adder and multiplier, reworked
Platform: | Size: 817152 | Author: Ivrine | Hits:

[Other] Comparative study of FFA architectures using different multiplier and adder topologies

Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
Platform: | Size: 1123027 | Author: nalevihtkas | Hits:
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